In semiconductor devices comprising MOS devices such as MOS transistors as basic constituent elements, those in which MOS devices of different required performances such as memory cells and peripheral circuits, digital circuits and analog circuits, and devices requiring high speed operation and devices requiring low power consumption operation are present together have been used more and more. For satisfying respective required performances for different MOS devices, it is effective to form plural types of MOS devices having gate dielectrics different from each other. The technique for attaining the same includes, for example, a multi-level gate dielectric technique. Semiconductor devices having plural MOS devices formed by disposing silicon dioxides of multi-level thickness together have been generally mass produced.
Now, description is to be made to an example of the prior art of forming two types of gate dielectrics comprising two levels of thickness with reference to FIGS. 8A to 8G. After forming an isolation trench 2 by using well-known shallow trench isolation on the surface of a silicon substrate 1, a silicon dioxide 3 of 7.7 nm thickness is formed on the silicon substrate 1 at 800° C. by pyrogenic oxidation while flowing oxygen at 10 liter/min and hydrogen at 0.5 liter/min simultaneously (FIG. 8A).
Then, a resist 4 is coated over the entire wafer surface (FIG. 8B), and usual pattering is conducted to remove a portion of the resist (FIG. 8C). The substrate 1 is divided at this step into a domain 1 for a portion covered with the resist 4 and a domain 2 for a portion not covered with the resist 4.
Successively, the gate dielectric 3 in the domain 2 is removed by a diluted HF solution (FIG. 8D) and then the resist 4 is dissolved and removed by an aqueous solution containing H2SO4 and H2O2 (FIG. 8E). Subsequently, cleaning with an aqueous solution containing NH3 and H2O2 (hereinafter referred to as “SC-1 cleaning”) and cleaning with an aqueous solution containing HCl and H2O2 (hereinafter referred to as “SC-2 cleaning”) are conducted to remove contaminations on the surface. Further, after conducting the SC-1 cleaning and cleaning with the diluted HF solution, pyrogenic oxidation is conducted at 800° C. to form a gate dielectric 5 which is a silicon dioxide of 4 nm thickness and a gate dielectric 6 which is a silicon oxide of 8 nm thickness.
By the way, decrease of the thickness of the gate dielectric has been progressed rapidly in recent years in view of the demand for higher speed operation or lower voltage operation of MOS devices. As a result, a problem of increasing current that leaks through the dielectric film, that is, agate leak current and a problem of diffusion of boron (B) in the gate electrode through the gate dielectric to a silicon substrate have become conspicuous. In a case of forming multi-level thickness gate dielectrics, the problems are conspicuous naturally in the gate dielectric of least thickness.
A countermeasure for preventing increase of the gate leak current or B diffusion includes a method of introducing nitrogen by heat treating a silicon dioxide in a nitrous oxide (N2O) gas or nitric oxide (NO) gas atmosphere disclosed, for example, in a first document: U.S. document: “IEDM Technical Digest”, page 691 (issued in 1995) and this has already been adopted in mass production.
Further, as the thickness of the gate dielectric is decreased to 2 nm or less as the equivalent oxide thickness converted from the electric capacitance, the problem of gate leak current or B diffusion becomes more stringent. In this case, it is demanded for a gate dielectric comprising an SI—O—N ternary system material having higher nitrogen concentration, and a method of treating the silicon dioxide by using an active nitrogen is disclosed, for example, in a second document: US and Japanese documents “Symposium on VLSI Technology Digest of Technical Papers”, page 116 (issued in 2000). By the method described above, greater amount of nitrogen is introduced into the silicon dioxide compared with the method of using a heat treatment in the N2O gas or NO gas atmosphere.
On the other hand, for decreasing the thickness of the gate dielectric, with a view point of preventing degradation in the uniformity of thickness of the silicon dioxide and heavy metal contamination caused by the resist of the silicon dioxide, apart from the view point of suppressing the gate leak current or B diffusion by the decrease of the thickness for the gate dielectric, a method of forming a gate dielectric comprising silicon nitride as a base structure is disclosed, for example, in a third document: Japanese Patent Laid-Open No. 2001-7217.
According to the third document, the gate dielectric with silicon nitride is formed as described below. As shown in FIGS. 9A to 9C, a well layer 94 is formed on a silicon substrate 91 and, after further forming a device isolation dielectric layer 92 selectively, a silicon nitride film 95 is formed over the entire region with no device isolation dielectric layer 92 (FIG. 9A), and a nitride film 95 is removed selectively using a resist as a mask (FIG. 9B). Then, a heat treatment is conducted in an oxidative atmosphere, a silicon dioxide is formed to a region removed with the silicon nitride film 95 and, at the same time, a film formed by thermally oxidizing the silicon nitride film is formed in a region where the silicon nitride film 95 is left and they are used, respectively, as gate dielectrics 98 and 97 (FIG. 9C)